Phase-change random access memories (PRAMs) are non-volatile memories that store data using materials, such as Ge—Sb—Te (GST) and/other phase-change materials, in which the resistance may change upon transition between amorphous and crystalline states, for example, due to a change in temperature. PRAMs may offer non-volatility and lower power consumption in addition to the advantages of dynamic random access memories (DRAMs), and thus may be regarded as a next generation memory.
FIG. 1 is an equivalent circuit diagram of a unit cell C of a PRAM device.
FIG. 2 is a cross-sectional view of a memory device ME including the phase-change material GST of FIG. 1.
Referring to FIGS. 1 and 2, the unit cell C of the PRAM device includes the memory device ME and a P-N diode D. A bit line BL is connected to the phase-change material GST which is connected to a P-junction of the P-N diode D, and a word line WL is connected to an N-junction of the P-N diode D. Alternatively, the PRAM device may include a transistor (not shown) connected to the phase-change material GST instead of the P-N diode D.
The memory device ME includes the phase-change material GST. A phase-change material (Ge—Sb—Tb) of a PRAM cell may transition between a crystalline state and an amorphous state depending on the temperature and/or duration of heating applied to the phase-change material, thereby storing data in the PRAM cell. In general, a temperature above about 900° C. may be required for a phase transition of the phase-change material. Such high temperatures may be obtained by Joule heating caused by current flowing through the PRAM cell.
If the current is supplied to a bottom electrode BEC of the memory device ME, the volume and state of a PGM, e.g., a contact region between the phase-change material GST and the bottom electrode BEC, is changed so as to provide the state of the phase-change material GST.
FIG. 3 is a graph illustrating the characteristics of the phase-change material GST of FIGS. 1 and 2. Here, “CON1” indicates conditions for changing the phase-change material GST to an amorphous state, and “CON0” indicates conditions for changing the phase-change material GST to a crystalline state. Referring to FIGS. 1 to 3, a write operation and a read operation of the PRAM device will be described.
First, a write operation will be described. In order to store data “1”, the phase-change material GST is heated to a temperature above its melting temperature TMP2 (t1), and then rapidly cooled. Then, the phase-change material GST goes into an amorphous state defined as data “1” and referred to as a reset state. In order to store data “0”, the phase-change material GST is heated to a temperature above its crystalline temperature TMP1 for a predetermined period of time (t2), and gradually cooled. Then, the phase-change material GST goes into a crystalline state defined as data “0” and referred to as a set state.
Next, a read operation will be described. The bit line BL and the word line WL are selected in order to select a memory cell C that is to be read. A read current is supplied to the selected memory cell C to determine whether data stored in the selected memory cell C is “1” or “0”, based on a voltage change caused by a resistance of the phase-change material GST of the selected memory cell C. The resistance of the memory cell C may differ based on whether the phase change material GST is in the amorphous or crystalline state.
Cell defects may cause operational errors in a highly integrated PRAM, and thus, a redundancy cell array may be used to compensate for the cell defects. However, access to redundant cells may require a longer time than access to normal cells in banks during redundancy cell test operations since the number of input/output lines used to transmit test data may be limited. Furthermore, a redundancy cell test may require considerably more time than a conventional cell test.